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Security and Robustness for Intermittent Computing Using Cross-Layer Post-CMOS Approaches

The realization of resource-limited, normally-off energy harvesting devices has impacted a wide range of Internet of Things (IoT) applications such as wearable devices, remote sensing, and industrial systems. Nevertheless, these devices are typically exposed to various existing and new vulnerabilities, including physical attacks, such as side-channels and magnetic attacks, unanticipated power outages and power failures, and other unique vulnerabilities. Exploiting these vulnerabilities could lead to irreparable damage to property and lives because of the large number of connected nodes/devices. The available defense schemes against these attacks either have high overheads, which make them inapplicable to resource-constrained nodes, or incomplete. 

To address these shortcomings, our research aims to develop comprehensive yet lightweight security strategies. Specifically, our objective is to ensure secure, intermittent-robust computation for these resource-constrained, normally-off computing nodes. We plan to achieve this by leveraging emerging, non-volatile, spin-based devices to construct reconfigurable logic circuits that are both lightweight and secure. Our approach centers on ensuring that computations can continue robustly even in the face of various types of attacks. This is made possible by storing intermediate computational states within non-volatile (NV) devices. Additionally, we aim to innovate new techniques that synergize circuit design, architectural paradigms, and algorithmic methods. These new techniques not only bolster the system’s resilience against attacks but also minimize the resource overhead, making the solution both effective and efficient. By achieving this objective, we aspire to set a new benchmark in the realm of secure computing for IoT applications, thereby ensuring a safer and more reliable digital future.


 Cross-Layer Solutions Enabling Instant Computing for Edge Intelligence Devices

This project crosscuts multiple levels of design abstraction to realize low-cost and efficient design strategies for real-time processing and decision-making systems, including:
(1) Designing and analyzing low-power area-efficient integrated converter, including Binary-to-Residue Number System (RNS) and Analog-to-Digital Converter (ADC);
(2) Proposing a new reconfigurable near-sensor RNS processing unit (RPU) to accelerate low-bit-width (quantized) neural networks, realizing IoT devices with intelligence. The RPU architecture enables performing MAC with only one-cycle latency and no sacrifice of existing memory function and capacity, also handling the activation, pooling, and normalization layers. The obtained non-von-Neumann architecture, namely Residual co-Processor (RcP), co-integrates conversion and processing capabilities in conjunction with an unconventional number system.
(3) Designing an automated exploration tool entitled Residual Architecture Search (RAS) to find the optimal architecture of processing units for both generic computations and domain-specific and emerging applications; we quantify how our methods improve metrics such as lifetime energy reduction, resiliency, and overall performance; and 
(4) Developing a comprehensive cross-layer evaluation framework, including FPGA-magnetic RAM-based prototypes for various energy-hungry applications and evaluating the generated architectures in conjunction with RISC-V-based processors using real-world IoT applications.


Integrated Sensing and Normally-off Computing for Edge Imaging Systems

Internet of Things (IoT) devices are projected to attain an $1100B market by 2025, with a web of interconnection projected to comprise approximately 75+ billion IoT devices.
The large number of IoTs consist of sensory imaging systems that enable massive data collection from the environment and people. However, considerable portions of the captured sensory data are redundant and unstructured. Data conversion of such large raw data, storing in volatile memories, transmission, and computation in on-/off-chip processors impose high energy consumption, latency, and a memory bottleneck at the edge. 
Moreover, because renewing batteries for IoT devices is very costly and sometimes impracticable, energy-harvesting devices with ambient energy sources and low maintenance have impacted a wide range of IoT applications, such as wearable devices, smart cities, and the intelligent industry.

Considering these challenges, there's a clear and pressing need for the exploration and development of computing architectures that are high-speed, consume minimal power, and can remain off under normal conditions. Our primary goal is to foster integrated sensing computation for these resource-limited sensory nodes, diving deep into cross-layer post-CMOS methodologies. Our approach amalgamates the benefits of always-on sensing with the efficiency of normally-off computing. By synergizing innovations from both circuit design and architectural strategies and harnessing the potential of emerging non-volatile devices, we aim to redefine the landscape of IoT device operations. Furthermore, to ensure that our sensory systems remain resilient even during power outages, we've incorporated a mechanism where intermediate circuit values are securely stored in non-volatile devices, ensuring intermittent-robust computation.


Ultra-Low Power In-Memory Computing:

Over past decades, the amount of data that is required to be processed and analyzed by the computing systems has been increasing dramatically to exascale, which brings grand challenges for state-of-the-art computing systems to simultaneously deliver energy-efficient and high-performance computing solutions. Such challenges mainly come from the well-known power wall (i.e. huge leakage power consumption limits the performance growth when technology scales down) and memory wall (including long memory access latency, limited memory bandwidth, and energy-hungry data transfer). Therefore, there is a great need to leverage innovations from both circuit design and computing architecture to build an energy-efficient and high-performance non-Von-Neumann computing platform. In-memory computing has been proposed as a promising solution to reduce massive power-hungry data traffic between computing and memory units, leading to significant improvement in entire system performance. My research focuses on: 

  • Explore various in-memory logic circuit designs based on existing memory technologies, including SRAM, DRAM, Magnetic (Spintronic) Memory, Resistive RAM, with low overhead, efficient operation, low latency, etc

  • Explore dual-mode in-memory computing architecture designs that could simultaneously work as memory and in-memory computing units to greatly reduce data communication, fully leverage the highly parallel computing ability of processing-in-memory architecture, and thus improve system performance

  • Explore suitable in-memory computing applications that could be either fully implemented or pre-processed in the proposed in-memory computing platform, including deep neural network, data encryption, image processing, graph processing, bioinformatics, etc

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