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Publication (2021-present)

Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence

IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) (best paper candidate)

Conference

PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal

Design and Evaluation of a Near-Sensor Magneto-Electric FET-Based Event Detector

IEEE Transactions on Electron Devices

Journal

PISA: A Non-Volatile Processing-In-Sensor Accelerator for Imaging Systems

IEEE Transactions on Emerging Topics in Computing

Journal

A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks

IEEE Transactions on Emerging Topics in Computing

Journal

SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP

Great Lakes Symposium on VLSI (GLSVLSI)

Conference

P-PIM: A Parallel Processing-in-DRAM Framework Enabling Row Hammer Protection

Design, Automation & Test in Europe Conference & Exhibition (DATE)

Conference

XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration

International Symposium on Quality Electronic Design (ISQED)

Conference

NeSe: Near-Sensor Event-Driven Scheme for Low Power Energy Harvesting Sensors

IEEE International Symposium on Circuits and Systems (ISCAS)

Conference

AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Journal

Design and evaluation of ultra‐fast 8‐bit approximate multipliers using novel multicolumn inexact compressors

International Journal of Circuit Theory and Applications

Journal

semiMul: Floating-Point Free Implementations for Efficient and Accurate Neural Network Training

EEE International Conference on Machine Learning and Applications (ICMLA)

Conference

LT-PIM: An LUT-based processing-in-DRAM architecture with RowHammer self-tracking

IEEE Computer Architecture Letters

Journal

HARDeNN: Hardware-assisted attack-resilient deep neural network architectures

Microprocessors and Microsystems

Journal

ReD-LUT: Reconfigurable in-DRAM LUTs enabling massive parallel computation

IEEE/ACM International Conference on Computer-Aided Design

Conference

Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks

Journal of Low Power Electronics and Applications

Journal

Toward a Behavioral-Level End-to-End Framework for Silicon Photonics Accelerators

International Green and Sustainable Computing Conference (IGSC)

Conference

TizBin: A low-power image sensor with event and object detection using efficient processing-in-pixel schemes

International Conference on Computer Design (ICCD)

Conference

Work-in-Progress: A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)

Conference

MR-PIPA: An Integrated Multilevel RRAM (HfOx)-Based Processing-In-Pixel Accelerator

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Journal

Enabling Edge Computing Using Emerging Memory Technologies: From Device to Architecture

Frontiers of Quality Electronic Design (QED) AI, IoT and Hardware Security

Book

Enabling intelligent iots for histopathology image analysis using convolutional neural networks

Micromachines

Journal

Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell

IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)

Conference

Enabling Efficient Training of Convolutional Neural Networks for Histopathology Images

International Conference on Image Analysis and Processing

Journal

Flexidram: A flexible in-dram framework to enable parallel general-purpose computation

ACM/IEEE International Symposium on Low Power Electronics and Design

Conference

Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network

IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

Conference

EaseMiss: HW/SW Co-Optimization for Efficient Large Matrix-Matrix Multiply Operations

IEEE 15th Dallas Circuit And System Conference (DCAS)

Conference

SCiMA: A Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations

IEEE International Symposium on Circuits and Systems (ISCAS)

Conference

Integrated sensing and computing using energy-efficient magnetic synapses

International Symposium on Quality Electronic Design (ISQED)

Conference

ReFACE: efficient design methodology for acceleration of digital filter implementations

International Symposium on Quality Electronic Design (ISQED)

Conference

RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems

IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Conference

Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study

Great Lakes Symposium on VLSI (GLSVLSI)

Conference

Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network

Asia and South Pacific Design Automation Conference (ASP-DAC)

Conference

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